Test for 4 Bit ADC and DAC
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A 4 Bit ADC and DAC test can be simulated in LTSPICE. The files were downloaded and LTSPICE simulation was started. The output file size can be limited by using the .save dialog option. A voltage source was added with a ramp from 0v to 1v with a rise time of 655µs. The picture shows a ramp input voltage and the DAc ramp output voltage over time. 16 step can be seen. With a measurement statement the voltage were extracted. .Measure TRAN V0000 FIND V(vout) AT=20u. At 60us time the output of 0.625v is given for the code 0001. V0001: V(vout)=0.0625 at 6e-005 No error in the voltage level can be seen. It is an idesl ADC and DAC. 
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LTSPICE schematics
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JavaScript module SPICE_HTML_2018_02/LTSPICE.js Canvas, Control, Link, Code parts Add schematics to processing list ID has to be the same as the schematic name. Transfer curve, INL and DNL are shown below. 
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Real output signal Shape.
Learning Outcomes and Challenges
I have learned: The basic technique to create or edit my own Webpage using HTML. How to attach image file. To include LTSPICE file that has direct link to the source file and can be upgraded automatically after saving and simulation. And measuring output singnal in LTSPICE simulation using ".meas" statement. Challenges My webpage was not able to locate the Spice file. My colleague addressed this problem and it was debugged by changing the configuration of Firefox - privacy.file_unique_origin. |